1. Field of the Invention
The present invention relates to the field of resistors integral with a semiconductor body, formed, for example, by diffusion or ion implantation into a single-crystal semiconductor substrate, typically of silicon. More particularly, the present invention relates to a method of correcting the voltage coefficient of resistance (VCR) in implanted resistors and the resistor structures resulting therefrom.
In the field of semiconductor electronics, circuit designers are relying more and more on the use of integrated circuit structures. These structures have developed at a rapid pace in recent years as a result of the many improvements made in basic active and/or passive components. Besides the active components such as transistors, diodes, etc., passive components, especially resistors, continue to play an essential role in many applications such as, for example, applications involving analog circuits. Two technologies can be used to associate resistors with active components in integrated circuits: one of these is the compatible hybrid technology wherein resistors are deposited in the form of thin films on the surface of an integrated semiconductor chip; the other is the monolithic technology in which the resistors are formed within the semiconductor chip itself in the same manner as the active components. In the latter case, the resistors can be formed either by thermal diffusion or by ion implantation.
Diffused resistors are well known in the art. These resistors are generally formed during the diffusion step of the base or emitter region of bipolar transistors. Conventionally, a P type base region is diffused into a N.sup.- type epitaxial layer which overlays a P.sup.- type single-crystal silicon substrate. The value of the resistor depends upon a number of parameters such as the profile and depth of the diffusions, the length-to-width ratio of the diffused zone, etc. Two ohmic contacts are formed at the ends of the diffused region and constitute the output terminals of the resistor. The most positive potential of the circuit is generally applied to that portion of the epitaxial layer which is located within the isolation pocket, which includes the resistive region. The limitations of such resistors are their low sheet resistance (400 .OMEGA./.quadrature.), the low accuracy of their nominal value (.+-.20%) and their high temperature coefficient (of the order of 2000 ppm/.degree.C.), resulting in a significant variation of the resistance as a function of the temperature: 10% between 25.degree. and 75.degree. C. On the other hand, the method of forming such resistors is well known and relatively simple to use.
Implanted resistors are a particularly interesting alternative to diffused resistors and offer significant advantages over the latter. In particular, boron implanted resistors exhibiting a wide range of sheet resistance values (3 to 10,000 .OMEGA./.quadrature. and over) and a low sensitivity to temperature (resistance variation of 0.5% between 0.degree. and 75.degree. C.) can be obtained. In addition, such resistors are relatively accurate and generally well matched (.+-.2%). This type of device is discussed in an article by K. Rosendal entitled "Ion Implanted Planar Resistors", in Radiation Effects, Vol. 7, pp. 95-100, Nos. 1 & 2, January 1971.
A comparative study of the three types of resistors mentioned above may be found in an article by J. Den Boer et al entitled "The Thermal Properties of High Value Gallium and Boron Implanted Resistors in Silicon", appearing in European Conference on Ion Implantation, Sept. 7-9, 1970.
2. Description of Problem and Prior Art
A problem to which little attention has been paid until recently, namely, the variation of the resistance value as a function of the voltage applied across the resistor, appears to be of growing importance. The I-V characteristic of a resistor should normally be linear. It has been found that this only holds true with respect to implanted resistors exhibiting a low sheet resistance of the order of a few hundred ohms/.quadrature.. This has been shown in an article by John McDougall et al entitled "High Value Implanted Resistors for Microcircuits" appearing in Proceedings of the IEEE, Vol. 57, No. 9, page 1540, September 1969, and, more particularly, as shown in FIG. 5 of this article.
If high value implanted resistors that require high sheet resistance values (e.g. 20 K.OMEGA./.quadrature.) are desired, the I-V characteristic becomes nonlinear and slopes downwards, causing the response of the resistor to an input signal to be distorted. This demonstrates that the actual value of the resistor at a given voltage is higher than the value measured with a very low voltage. The I-V characterstic is then in every way similar to that of a junction field effect transistor (JFET). It should be clearly understood that the value of the resistor is primarily a function of the voltage applied to the junction between the resistive region and the epitaxial layer. This value is to some extent related to the voltage V.sub.R across the resistor. The distortion is due to the fact that the depletion layer, located on both sides of the PN junction and devoid of charge carriers, tends to become wider as the voltage applied to the PN junction increases, thereby reducing the effective cross-section of the resistor and ultimately increasing its value. This is the well-known problem of pinch-off voltage which is associated, in particular, with JFETs, but is more critical with respect to implanted resistors than with respect to diffused resistors since implanted resistors generally exhibit higher resistivities and are consequently thinner and less doped.
A first solution to the pinch-off voltage problem is described in an article by John McDougall, supra, and involves increasing the resistivity of the epitaxial layer to achieve values higher than 100 ohms-cm. However, this can adversely affect some electrical parameters of adjacent active devices.
Another solution would be to limit the development of the depletion layer within the resistive region so as to decrease, as we have seen, the nominal value of the resistor. This can be achieved by increasing the ion dose, as described in an article by J. W. Hanson entitled "Ion Implanted N Type Resistors on High Resistivity Substrates", in J. Vac. Sci. Tech., Vol. 10, No. 6, November-December 1973, and more particularly as illustrated in FIG. 6 of that article.
Still another solution is proposed in French patent No. 71 44227 assigned to Philips. Although no specific reference to the VCR is made therein, it would seem that correction of the VCR can be achieved by implanting ions of neutral species in the resistive region, preferably in the vicinity of the PN junction. These crystal defect generating ions have the property of improving the linearity of the I-V characteristic of the resistor. In this regard, more particular reference should be made to FIG. 7 of this patent. The main disadvantage of this method is that it requires an additional process step.
Still a further solution is proposed in French Patent 76 15001 filed on May 13, 1976 and assigned to the assignee of the present invention. In its more general aspect, this patent describes means for controlling the variations of the potential difference between the resistive region and the epitaxial layer in order to minimize such variations. For this purpose, the potential of the epitaxial layer is brought to a suitable value, preferably a value that varies as the average value of the resistor to be corrected. If V.sub.1 and V.sub.2 are the potentials respectively applied to the two terminals of the resistor, the potential to be applied to the epitaxial layer takes the form: EQU V.sub.epi =1/2 (V.sub.1 +V.sub.2)+V.sub.0
where V.sub.0 is a continuous biasing potential. When using this particular value of V.sub.epi, the resistance becomes almost independent from the voltage applied to the terminals of resistor V.sub.R =V.sub.1 -V.sub.2. However, a serious drawback of this process consists in the fact that, for achieving an efficient compensation, it is necessary to provide an auxiliary circuit which applies the suitable biasing value to each epitaxial layer. It is clear that such a solution, after integration, consumes surface area on the chip and reduces integration density. In addition, the required auxiliary circuits typically may be unable to provide the desired performance, particularly as pertains to speed.